| Commit message (Collapse) | Author | Age |
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Gbp-Pq: Name 0007-Compatible-with-newer-opensta-version.patch
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Gbp-Pq: Name 0006-Fix-error-when-calling-opensta.sh.patch
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with a "+" in the version string. This patch fixes this.
Gbp-Pq: Name yosys_version_number_minor.patch
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Gbp-Pq: Name fix_tcsh_path.patch
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Gbp-Pq: Name 01_fix_install_dir.patch
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commit dc3fd38c211f20185d4ddc834675bfe5906409d1
Merge: 7e4ea8a 64c1647
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon Sep 19 08:57:53 2016 -0400
Merge branch 'master' into work
commit 64c164786167c99d866efd197f10020f846163dd
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Mon Sep 19 08:57:53 2016 -0400
Update at Mon Sep 19 08:57:53 EDT 2016 by tim
commit 7e4ea8a20d6cf368f06ab5dca57a7f84252ce9a9
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon Sep 19 08:57:05 2016 -0400
Applied patch by Risto Bell for Bugzilla bug 138.
commit e0cf18353ee42a42eec97dbf443e4df6a58eb070
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Sun Sep 18 22:17:54 2016 -0400
Corrected error in vesta that causes crash if no delay file is
specified.
commit 63b2233c4f5ae8f3453e59f839f140365b3d97ca
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Sun Sep 18 22:09:19 2016 -0400
Swapped the reading of <techname>.sh and project_vars.sh, so that
values in project_vars.sh may override those in <techname>.sh,
specifically for option strings passed to applications (like
blifFanout).
commit dbfe2219a3957e5f0770466d04a796bff991f129
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Sun Sep 18 21:53:47 2016 -0400
Fixed help text of blifFanout so that MaxFanout, which is integer,
is not printed with %g, and so that where values set by the
command line were referred to as 'default', these values are now
referred to as 'value', and the actual default value is also given.
commit 94d20b55ffd9104c99bce1d76f2a0eb46a3d1899
Merge: 3cb0d32 6b689d5
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Sun Sep 18 21:45:31 2016 -0400
Merge branch 'master' into work
commit 6b689d535ef4f1ebf3293c9f1de384d176654e34
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Sun Sep 18 21:45:30 2016 -0400
Update at Sun Sep 18 21:45:29 EDT 2016 by tim
commit 3cb0d32a4ff634056cb9ab0e439ca4507adf4dab
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Sun Sep 18 21:44:17 2016 -0400
Corrected qflow script to use "tcsh -f" instead of "tcsh" in the
first line of scripts generated for use in running qflow (e.g.,
qflow_exec.sh).
commit b09c09d83a0d30f0c883873a318589b98d3b52c1
Merge: cab0547 e0110d9
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu Sep 8 21:26:06 2016 -0400
Merge branch 'master' into work
commit e0110d94b21f58bcbd72939b8a03d780fd1bf258
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Thu Sep 8 21:26:04 2016 -0400
Update at Thu Sep 8 21:26:04 EDT 2016 by tim
commit cab0547183f795a21eb03d5d294381d0d415597c
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu Sep 8 21:24:27 2016 -0400
Added code for interconnect delay calculations from Russell
Friesenhahn.
commit 4d14dc5b35140e9cd2e47a4034b50fb865d65fc0
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu Jun 9 22:54:57 2016 -0400
Updated display script to generate a load script and run this from
the magic command-line, in conjunction with changes to magic to
allow scripts to be specified on the command line.
commit 2f33cdccdf19c40f57ce37e1ea3ba05af5f34cb1
Merge: bbda854 90c31df
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu Jun 9 08:55:48 2016 -0400
Merge branch 'master' into work
commit 90c31df4db7b38b723004c64470dce08180652c6
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Thu Jun 9 08:55:47 2016 -0400
Update at Thu Jun 9 08:55:47 EDT 2016 by tim
commit bbda854cabf54b28987ac4c848fb9c97e3f69e5b
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Thu Jun 9 08:55:13 2016 -0400
Corrected typo in display.sh; thanks to Santiago Rubio for pointing
it out.
commit 0f33d164b480fdfe221f0f073cb55942628ced3e
Merge: 696e8f4 709d00e
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Tue Jun 7 08:33:10 2016 -0400
Merge branch 'master' into work
commit 709d00e016c5605ea7ba5c101ff6004a55666391
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Tue Jun 7 08:33:09 2016 -0400
Update at Tue Jun 7 08:33:09 EDT 2016 by tim
commit 696e8f42f30335a4f9e5233926478d9021c7299b
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Tue Jun 7 08:31:38 2016 -0400
Corrected display script, as the embedded newline is not interpreted
correctly in the "lef read" command, and needs to be split into two
separate commands. Thanks to Santiago Rubio for the patch.
commit 0cb31415d634961e063f2b041b437fcae64b794f
Merge: dcb1baf 4c9d9f7
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon Apr 18 21:24:21 2016 -0400
Merge branch 'master' into work
commit 4c9d9f7df33d7eff9c467cf203692f69f9a864e7
Author: Tim Edwards <tim@vivaldi.tim.linglan.net>
Date: Mon Apr 18 21:24:20 2016 -0400
Update at Mon Apr 18 21:24:20 EDT 2016 by tim
commit dcb1bafa159647992b91a34f0b5e178f31602eea
Author: Tim Edwards <tim@opencircuitdesign.com>
Date: Mon Apr 18 21:18:54 2016 -0400
Modified the osu018 technology to use SCN6M_SUBM.10 instead of
SCN6M_DEEP.09; thanks to Shimon for pointing out that the OSU
standard cells matched the SUBM tech and not the DEEP. Otherwise,
reading the GDS files from the OSU018 standard cell set into
magic under SCN6M_DEEP.09 will generate large numbers of DRC
errors. Note, however, that the LEF files from OSU018 do not
specify metal extensions on the vias, and so stacked vias m1-m3
will cause minimum metal violations on metal2. The way around
this is to specify via stacks = 1 to qrouter, so that every
metal layer must route for at least 1 track width, which satisfies
the minimum metal requirement.
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without breaking, although the option is non-functional.
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strings returned by yosys.
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synthesize.sh so that removing the log file does not generate
an error message.
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the decongest script. This would cause overlap of cells when
cells have odd-numbered widths, leading to cell X positions that
precess relative to the routing grid along the width of the
layout.
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deal with a latch that it thought was a flop. Also, modified
blifFanout to give more relevant diagnostic information, such as
units used for loads and latencies, and showing how "strength"
relates to the specified maximum latency. Defaults for blifFanout
made more realistic, especially for the default 0.35um technology,
so that it doesn't constantly report that gates are too weak and
try to change all gates to the maximum size. Option "-f" changed
to "-I" ("I" for "Ignore") so that "-f" means do fanout buffering
only, and "-L" means do load balancing only.
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error if a route is given in the info file with a width or pitch
of zero. Simultaneous change to qrouter behavior should not let
such routes get into the info file, though. This check has
been added to qflow as a precautionary measure only.
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yosys. Specifically, yosys calls yosys-abc, which if not in the
standard search path, must be specified using the "-exe" switch
to the "abc" command in yosys.
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the addspacers tool was run, leading to different file contents.
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output filenames. Placement now copies the .def solution to
_unroute.def (previously done only at the end of the router
script). The router script uses the _unroute.def file as
input and does not overwrite it. The previous method allowed
the _unroute.def file to become out of sync with the rest of
the files.
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project_vars.sh, so that specific arguments can be passed to
graywolf. "-n" will disable graphics, allowing a fully
graphics-free flow.
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"yosys_debug" and the non-debug behavior is the default
(resulting in smaller layouts with fewer unconnected outputs
that are useful only for debugging).
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properly using the information from the info file to place pins
on 1-of-N route tracks when the layer width and spacing rules
require it.
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process RTL in the verilog source, but only added it to the
preliminary yosys script, not to the final one.
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the placement script, not the synthesis script. The change is
required due to the introduction of density planning, since the
density affects the generation of the .cel file passed to
graywolf for placement. If the .cel file is generated as part
of the synthesis script, then if the density is modified, the
flow has to be re-run from synthesis, not from placement. This
update corrects the issue.
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script that does not handle the case of zero fill cells, and so
was preventing densities above about 0.9 (one fill cell per
standard cell).
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synthesis flow scripts.
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techlef, gds, spice, liberty) can be specified as absolute
paths and not have to be symbolic links from the tech directory.
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was an incorrect computation of the number of fill cells to make
up the total density, resulting in fill cells being added even
if the density was set to 1. The other was a round-off error
resulting in an incorrect width value, which tends to cause bad
route failures.
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failure to find a verilog source file. Helps to catch and
resolve gross errors faster.
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to ABC that works much better than the default behavior, expanding
the range of cells used (e.g., will use AOI and OAI cells instead
of trying to shove everything into NAND/NOR logic). The practical
impact appears to be an increase in circuit speed as well as
routing efficiency. Added an additional hook from variable
"abc_script" in project_vars.sh for manual control over this
expression. 'set abc_script = ""' reverts to the original
behavior.
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the number of fill cells is less than the total number of cells,
due to having only large filler cells in the standard cell set.
Optimized "decongest" to make use of smaller fill cells if
available, such that the fill cells will outnumber the standard
cells, making the decongestion more evenly spread across the
layout. Improved blif2cel.tcl so that cells that only use
POLYGON for pins instead of RECT will not lose information
in the .cel file.
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that a route should go from a pin to both top and bottom of a cell,
and that putting these redundant net entries into the DEF file
output causes qrouter to report false failures. Rewrote the
place2def script to avoid generating the redundant entries.
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correct path to "tclsh" on installation.
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compile.
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Corrected synthesis script to no longer require a "gate.cfg" file
to run blifFanout, since this has been deprecated (and is no longer
in the set of installed files). Modified blifFanout to use the
first buffer found in the liberty file, so details of the buffer
cell do not need to be provided in the tech shell script (although
they will be used, if passed to the program).
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If set to 1, the yosys script uses "clean -purge" after the
standard cell mapping. This removes all the buffers that are
used to maintain internal signal names, resulting in a smaller
but less easily debugged layout.
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"synth -top <rootname>" command, for yosys versions 0.5 and up.
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