diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-06-12 11:54:20 +0200 |
commit | 482d9208aa9dacb7afe21f08c882d4881581013a (patch) | |
tree | a5a4d409f7d84cc2dc6283dcf45df3aea02cb061 /frontends/verilog/verilog_frontend.h | |
parent | 9a6cd64fc2ca46c9aed1bd03b6898c7734420c53 (diff) |
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
Diffstat (limited to 'frontends/verilog/verilog_frontend.h')
-rw-r--r-- | frontends/verilog/verilog_frontend.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h index 99b2164e..6d01a153 100644 --- a/frontends/verilog/verilog_frontend.h +++ b/frontends/verilog/verilog_frontend.h @@ -45,6 +45,9 @@ namespace VERILOG_FRONTEND // state of `default_nettype extern bool default_nettype_wire; + + // running in SystemVerilog mode + extern bool sv_mode; } // the pre-processor |