diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
| commit | 8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch) | |
| tree | 4da0980333589d4785880e48383c6f44e4a94887 /manual/CHAPTER_CellLib.tex | |
| parent | b9cb483f3e2a498ee75a422e09164a920918362b (diff) | |
Removed $bu0 cell type
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 82473f6a..5045960c 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -97,12 +97,6 @@ The width of the output port \B{Y}. Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators. -The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always -extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments -with {\tt x}-bits if the most significant bit is {\tt x}.) This is used -internally to correctly implement the {\tt ==} and {\tt !=} operators for -constant arguments. - \subsection{Multiplexers} Multiplexers are generated by the Verilog HDL frontend for {\tt |