diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-02 17:57:14 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-02 17:57:14 +0100 |
| commit | 6983d3f10bc526c51803107efa98e6d16353b414 (patch) | |
| tree | 00076529688deb5e4720a887594642de65800359 /manual/PRESENTATION_ExSyn | |
| parent | aa732b0c73ba16c1eb16f368eb8414c4ddda7bbc (diff) | |
presentation progress
Diffstat (limited to 'manual/PRESENTATION_ExSyn')
| -rw-r--r-- | manual/PRESENTATION_ExSyn/.gitignore | 1 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/Makefile | 12 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_00.v | 7 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_00.ys | 3 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_01.v | 8 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_01.ys | 3 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_02.v | 10 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_02.ys | 3 |
8 files changed, 47 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExSyn/.gitignore b/manual/PRESENTATION_ExSyn/.gitignore new file mode 100644 index 00000000..cf658897 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/.gitignore @@ -0,0 +1 @@ +*.dot diff --git a/manual/PRESENTATION_ExSyn/Makefile b/manual/PRESENTATION_ExSyn/Makefile new file mode 100644 index 00000000..0450075d --- /dev/null +++ b/manual/PRESENTATION_ExSyn/Makefile @@ -0,0 +1,12 @@ + +all: proc_00.pdf proc_01.pdf proc_02.pdf + +proc_00.pdf: proc_00.v proc_00.ys + ../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf' + +proc_01.pdf: proc_01.v proc_01.ys + ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' + +proc_02.pdf: proc_02.v proc_02.ys + ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' + diff --git a/manual/PRESENTATION_ExSyn/proc_00.v b/manual/PRESENTATION_ExSyn/proc_00.v new file mode 100644 index 00000000..61286319 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_00.v @@ -0,0 +1,7 @@ +module test(input D, C, R, output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= 0; + else + Q <= D; +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_00.ys b/manual/PRESENTATION_ExSyn/proc_00.ys new file mode 100644 index 00000000..6440efd3 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_00.ys @@ -0,0 +1,3 @@ +read_verilog proc_00.v +hierarchy -check -top test +proc;; diff --git a/manual/PRESENTATION_ExSyn/proc_01.v b/manual/PRESENTATION_ExSyn/proc_01.v new file mode 100644 index 00000000..8e440f6c --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_01.v @@ -0,0 +1,8 @@ +module test(input D, C, R, RV, + output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= RV; + else + Q <= D; +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_01.ys b/manual/PRESENTATION_ExSyn/proc_01.ys new file mode 100644 index 00000000..c22a2fd5 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_01.ys @@ -0,0 +1,3 @@ +read_verilog proc_01.v +hierarchy -check -top test +proc;; diff --git a/manual/PRESENTATION_ExSyn/proc_02.v b/manual/PRESENTATION_ExSyn/proc_02.v new file mode 100644 index 00000000..a89c965e --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_02.v @@ -0,0 +1,10 @@ +module test(input A, B, C, D, E, + output reg Y); + always @* begin + Y <= A; + if (B) + Y <= C; + if (D) + Y <= E; + end +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_02.ys b/manual/PRESENTATION_ExSyn/proc_02.ys new file mode 100644 index 00000000..823b18d6 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_02.ys @@ -0,0 +1,3 @@ +read_verilog proc_02.v +hierarchy -check -top test +proc;; |