diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 15:01:12 +0100 |
| commit | 295e352ba6aa1bd71431abc21a8f93735968cae6 (patch) | |
| tree | 2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /passes/cmds/add.cc | |
| parent | c854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff) | |
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'passes/cmds/add.cc')
| -rw-r--r-- | passes/cmds/add.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 12706c4f..acee4c46 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -73,7 +73,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n RTLIL::Module *mod = design->modules.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; - if (mod->get_bool_attribute("\\placeholder")) + if (mod->get_bool_attribute("\\blackbox")) continue; if (it.second->connections.count(name) > 0) continue; @@ -144,7 +144,7 @@ struct AddPass : public Pass { RTLIL::Module *module = mod.second; if (!design->selected_whole_module(module->name)) continue; - if (module->get_bool_attribute("\\placeholder")) + if (module->get_bool_attribute("\\blackbox")) continue; if (command == "wire") |