diff options
author | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
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committer | Ahmed Irfan <irfan@levert.(none)> | 2015-04-03 16:38:07 +0200 |
commit | bdf6b2b19ab2206f5957ad5b2ec582c2730d45ee (patch) | |
tree | 1d02541701054a1c3b1cdb66478d0cbc31c2d38f /passes/cmds/rename.cc | |
parent | 8acdd90bc918b780ad45cdac42b3baf84d2cc476 (diff) | |
parent | 4b4490761949e738dee54bdfc52e080e0a5c9067 (diff) |
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Diffstat (limited to 'passes/cmds/rename.cc')
-rw-r--r-- | passes/cmds/rename.cc | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index 91de364f..17d803e9 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -21,6 +21,9 @@ #include "kernel/rtlil.h" #include "kernel/log.h" +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name) { from_name = RTLIL::escape_id(from_name); @@ -31,8 +34,11 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: for (auto &it : module->wires_) if (it.first == from_name) { - log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); - module->rename(it.second, to_name); + Wire *w = it.second; + log("Renaming wire %s to %s in module %s.\n", log_id(w), log_id(to_name), log_id(module)); + module->rename(w, to_name); + if (w->port_id) + module->fixup_ports(); return; } @@ -113,7 +119,7 @@ struct RenamePass : public Pass { if (!design->selected(module)) continue; - std::map<RTLIL::IdString, RTLIL::Wire*> new_wires; + dict<RTLIL::IdString, RTLIL::Wire*> new_wires; for (auto &it : module->wires_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); @@ -121,8 +127,9 @@ struct RenamePass : public Pass { new_wires[it.second->name] = it.second; } module->wires_.swap(new_wires); + module->fixup_ports(); - std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; + dict<RTLIL::IdString, RTLIL::Cell*> new_cells; for (auto &it : module->cells_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str()); @@ -143,7 +150,7 @@ struct RenamePass : public Pass { if (!design->selected(module)) continue; - std::map<RTLIL::IdString, RTLIL::Wire*> new_wires; + dict<RTLIL::IdString, RTLIL::Wire*> new_wires; for (auto &it : module->wires_) { if (design->selected(module, it.second)) if (it.first[0] == '\\' && it.second->port_id == 0) @@ -151,8 +158,9 @@ struct RenamePass : public Pass { new_wires[it.second->name] = it.second; } module->wires_.swap(new_wires); + module->fixup_ports(); - std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; + dict<RTLIL::IdString, RTLIL::Cell*> new_cells; for (auto &it : module->cells_) { if (design->selected(module, it.second)) if (it.first[0] == '\\') @@ -196,3 +204,4 @@ struct RenamePass : public Pass { } } RenamePass; +PRIVATE_NAMESPACE_END |