path: root/passes/cmds/
Commit message (Expand)AuthorAge
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added design->rename(module, new_name)Clifford Wolf2015-06-30
* Added "rename -top new_name"Clifford Wolf2015-06-17
* Fixed iterator invalidation bug in "rename" commandClifford Wolf2015-02-09
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-26
* Added missing fixup_ports() calls to "rename" commandClifford Wolf2014-11-08
* namespace YosysClifford Wolf2014-09-27
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Added "rename -hide" commandClifford Wolf2014-01-02
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-07
* Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-19
* Added "rename" commandClifford Wolf2013-06-10