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rename.cc
Commit message (
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Author
Age
*
Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Added design->rename(module, new_name)
Clifford Wolf
2015-06-30
*
Added "rename -top new_name"
Clifford Wolf
2015-06-17
*
Fixed iterator invalidation bug in "rename" command
Clifford Wolf
2015-02-09
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
*
Added missing fixup_ports() calls to "rename" command
Clifford Wolf
2014-11-08
*
namespace Yosys
Clifford Wolf
2014-09-27
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Implemented "rename -enumerate -pattern"
Clifford Wolf
2014-08-26
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added "rename -hide" command
Clifford Wolf
2014-01-02
*
Improved handling of private names in opt_clean and rename commands
Clifford Wolf
2013-08-07
*
Added renaming of wires and cells to "rename" command
Clifford Wolf
2013-06-19
*
Added "rename" command
Clifford Wolf
2013-06-10