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authorClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-14 10:56:05 +0200
commit84bf862f7c58c2b69babf043ff5032f924a3ee4d (patch)
treec19a405bc106c2472f1aaa46c36b189db3e5223f /passes/cmds/splice.cc
parent80910d13a610886f4430fbd991ada78b2e586ada (diff)
Spell check (by Larry Doolittle)
Diffstat (limited to 'passes/cmds/splice.cc')
-rw-r--r--passes/cmds/splice.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index e56699f4..4ce2ec11 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -255,7 +255,7 @@ struct SplicePass : public Pass {
log("\n");
log("This command adds $slice and $concat cells to the design to make the splicing\n");
log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
- log("synthesis, where dedidacted hardware is needed to splice signals.\n");
+ log("synthesis, where dedicated hardware is needed to splice signals.\n");
log("\n");
log(" -sel_by_cell\n");
log(" only select the cell ports to rewire by the cell. if the selection\n");