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splice.cc
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*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
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Squashed commit of the following:
Ruben Undheim
2016-09-23
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renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added "splice -wires"
Clifford Wolf
2015-04-13
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Fixed memory corruption in "splice" command
Clifford Wolf
2014-12-29
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namespace Yosys
Clifford Wolf
2014-09-27
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Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
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Added various new options to splice command
Clifford Wolf
2014-02-08
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Now also move net labes to the right position in splice cmd
Clifford Wolf
2014-02-08
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Added splice command
Clifford Wolf
2014-02-07