Imported yosys 0.7

1 files changed, 29 insertions, 0 deletions

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 922a47ca..2c4db1ac 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1334,6 +1334,18 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$anyseq (Y);
+
+parameter WIDTH = 0;
+
+output [WIDTH-1:0] Y;
+
+assign Y = 'bx;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$equiv (A, B, Y);
 
 input A, B;
@@ -1382,6 +1394,23 @@ endmodule
 
 `endif
 // --------------------------------------------------------
+`ifdef SIMLIB_FF
+
+module \$ff (D, Q);
+
+parameter WIDTH = 0;
+
+input [WIDTH-1:0] D;
+output reg [WIDTH-1:0] Q;
+
+always @($global_clk) begin
+	Q <= D;
+end
+
+endmodule
+
+`endif
+// --------------------------------------------------------
 
 module \$dff (CLK, D, Q);