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| author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
| commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
| tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/asicworld/code_hdl_models_half_adder_gates.v | |
initial import
Diffstat (limited to 'tests/asicworld/code_hdl_models_half_adder_gates.v')
| -rw-r--r-- | tests/asicworld/code_hdl_models_half_adder_gates.v | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/asicworld/code_hdl_models_half_adder_gates.v b/tests/asicworld/code_hdl_models_half_adder_gates.v new file mode 100644 index 00000000..6acf243f --- /dev/null +++ b/tests/asicworld/code_hdl_models_half_adder_gates.v @@ -0,0 +1,14 @@ +//----------------------------------------------------- +// Design Name : half_adder_gates +// File Name : half_adder_gates.v +// Function : CCITT Serial CRC +// Coder : Deepak Kumar Tala +//----------------------------------------------------- +module half_adder_gates(x,y,sum,carry); +input x,y; +output sum,carry; + +and U_carry (carry,x,y); +xor U_sum (sum,x,y); + +endmodule |