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-rw-r--r--techlibs/xilinx/cells_sim.v6
1 files changed, 5 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 285d63db..c7f07e40 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -19,7 +19,7 @@ module OBUF(output O, input I);
assign O = I;
endmodule
-module BUFGP(output O, input I);
+module BUFG(output O, input I);
assign O = I;
endmodule
@@ -27,6 +27,10 @@ module OBUFT(output O, input I, T);
assign O = T ? 1'bz : I;
endmodule
+module IOBUF(inout IO, output O, input I, T);
+ assign O = IO, IO = T ? 1'bz : I;
+endmodule
+
module INV(output O, input I);
assign O = !I;
endmodule