path: root/techlibs/xilinx/cells_sim.v
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* Imported GIT HEAD: 0.8+20190328git32bd0f2Ruben Undheim2019-03-28
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-04
* Added Xilinx example for Basys3 boardClifford Wolf2015-02-01
* Fixed xilinx FDSE sim modelClifford Wolf2015-01-24
* Added MUXCY and XORCY support to synth_xilinxClifford Wolf2015-01-17
* Added FF cells to xilinx/cells_sim.vClifford Wolf2015-01-16
* added minimalistic xilinx sim modelsClifford Wolf2015-01-08