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Age
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Added support for global tasks and functions
Clifford Wolf
2014-08-21
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Using "via_celltype" in $mul carry-save-acc implementation
Clifford Wolf
2014-08-18
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Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
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Performance fix for new $__lcu techmap rule
Clifford Wolf
2014-08-18
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Replaced recursive lcu scheme with bk adder
Clifford Wolf
2014-08-18
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Added const folding of AST_CASE to AST simplifier
Clifford Wolf
2014-08-18
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Fixed proc_{self,share}_dirname error handling
Clifford Wolf
2014-08-17
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Makefile fixes
Clifford Wolf
2014-08-17
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Improved AST ProcessGenerator performance
Clifford Wolf
2014-08-17
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Improved sig.remove2() performance
Clifford Wolf
2014-08-17
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Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
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Added stackmap<> container
Clifford Wolf
2014-08-17
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Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
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Added module->uniquify()
Clifford Wolf
2014-08-16
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Fixed AOI/OAI expr handling in verilog backend
Clifford Wolf
2014-08-16
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Multiply using a carry-save accumulator
Clifford Wolf
2014-08-16
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Added "test_cell -s <seed>"
Clifford Wolf
2014-08-16
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AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf
2014-08-16
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Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵
Clifford Wolf
2014-08-16
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$_OAI4_
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Added CellTypes::cell_evaluable()
Clifford Wolf
2014-08-16
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Changes in techmap $__alu interface
Clifford Wolf
2014-08-16
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Added "opt -fast"
Clifford Wolf
2014-08-16
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Added log_spacer()
Clifford Wolf
2014-08-16
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Bugfix in iopadmap
Clifford Wolf
2014-08-15
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Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
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Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
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Removed old doc references to $safe_pmux
Clifford Wolf
2014-08-15
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More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
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Added Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf
2014-08-15
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document "techmap -map %<design-name>"
Clifford Wolf
2014-08-15
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Fixed bug in "read_verilog -ignore_redef"
Clifford Wolf
2014-08-15
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Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
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Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
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Added sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf
2014-08-14
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Fixed line numbers when using here-doc macros
Clifford Wolf
2014-08-14
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Fixed handling of task outputs
Clifford Wolf
2014-08-14
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Simplified $__arraymul techmap rule
Clifford Wolf
2014-08-14
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Added module->ports
Clifford Wolf
2014-08-14
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Refactoring of CellType class
Clifford Wolf
2014-08-14
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RIP $safe_pmux
Clifford Wolf
2014-08-14
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Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
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Added "abc -D" for setting delay target
Clifford Wolf
2014-08-14
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Updated ABC to 4935c2b946de
Clifford Wolf
2014-08-14
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Added techmap support for actual lookahead carry unit
Clifford Wolf
2014-08-13
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Preparations for lookahead ALU support in techmap.v
Clifford Wolf
2014-08-13
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Filter ANSI escape sequences from ABC output
Clifford Wolf
2014-08-13
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New interface for $__alu in techmap.v
Clifford Wolf
2014-08-13
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Added support for non-standard """ macro bodies
Clifford Wolf
2014-08-13
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Fixed handling of constant-true branches in proc_clean
Clifford Wolf
2014-08-12
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Added test_verific mode to tests/fsm/generate.py
Clifford Wolf
2014-08-12
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