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*
Removed undef feature from ezsat api
Clifford Wolf
2013-11-25
*
Using simplemap mappers from techmap
Clifford Wolf
2013-11-24
*
Added simplemap pass
Clifford Wolf
2013-11-24
*
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
Clifford Wolf
2013-11-24
*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
*
Added techmap -D and -I options
Clifford Wolf
2013-11-24
*
Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
*
Added "techmap -share_map" option
Clifford Wolf
2013-11-24
*
Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
*
Updated TODOs
Clifford Wolf
2013-11-24
*
Fixed xilinx/example_sim_counter test bench
Clifford Wolf
2013-11-24
*
Added proper dumping of signed/unsigned parameters to verilog backend
Clifford Wolf
2013-11-24
*
Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
*
Removed now obsolete test cases
Clifford Wolf
2013-11-24
*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
*
Added modelsim support to autotest
Clifford Wolf
2013-11-24
*
Fixed "flatten" top-module detection: Only use on fully selected designs
Clifford Wolf
2013-11-24
*
Fixed "make install" dependencies
Clifford Wolf
2013-11-24
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
*
Updated command-reference-manual.tex
Clifford Wolf
2013-11-23
*
AppNote 010 typo fixes and corrections
Clifford Wolf
2013-11-23
*
AppNote 010 progress
Clifford Wolf
2013-11-23
*
Improved handling of techmap special wires
Clifford Wolf
2013-11-23
*
Improved handling of initialized registers
Clifford Wolf
2013-11-23
*
Added more generic _TECHMAP_ wire mechanism to techmap pass
Clifford Wolf
2013-11-23
*
Making prograss on Appnote 010
Clifford Wolf
2013-11-23
*
Progress on AppNote 010
Clifford Wolf
2013-11-22
*
Started to write on AppNote 010: Verilog to BLIF
Clifford Wolf
2013-11-22
*
Updated command-reference-manual.tex
Clifford Wolf
2013-11-22
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Some driver changes/fixes
Clifford Wolf
2013-11-22
*
Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf
2013-11-22
*
Added more performance measurement infrastructure
Clifford Wolf
2013-11-22
*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ...
Clifford Wolf
2013-11-22
*
Massive performance improvement from refactoring RTLIL::SigSpec::optimize()
Clifford Wolf
2013-11-22
*
Added SigBit struct and refactored RTLIL::SigSpec::extract
Clifford Wolf
2013-11-22
*
Improved make rules for profiling and debugging
Clifford Wolf
2013-11-22
*
Updated abc
Clifford Wolf
2013-11-21
*
Implemented $_DFFSR_ expression generator in verilog backend
Clifford Wolf
2013-11-21
*
Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
*
Fixed a bug in "add -global_input"
Clifford Wolf
2013-11-21
*
Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
*
Fixed ilang parser: memory width
Clifford Wolf
2013-11-20
*
Added "add" command (only wires for now)
Clifford Wolf
2013-11-20
*
Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
*
Implemented indexed part selects
Clifford Wolf
2013-11-20
*
Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
*
Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf
2013-11-20
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