yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
...
* \|	Added support for global tasks and functions	Clifford Wolf	2014-08-21
\|/
*	Using "via_celltype" in $mul carry-save-acc implementation	Clifford Wolf	2014-08-18
\|
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
\|
*	Performance fix for new $__lcu techmap rule	Clifford Wolf	2014-08-18
\|
*	Replaced recursive lcu scheme with bk adder	Clifford Wolf	2014-08-18
\|
*	Added const folding of AST_CASE to AST simplifier	Clifford Wolf	2014-08-18
\|
*	Fixed proc_{self,share}_dirname error handling	Clifford Wolf	2014-08-17
\|
*	Makefile fixes	Clifford Wolf	2014-08-17
\|
*	Improved AST ProcessGenerator performance	Clifford Wolf	2014-08-17
\|
*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17
\|
*	Use stackmap<> in AST ProcessGenerator	Clifford Wolf	2014-08-17
\|
*	Added stackmap<> container	Clifford Wolf	2014-08-17
\|
*	Renamed toposort.h to utils.h	Clifford Wolf	2014-08-17
\|
*	Added module->uniquify()	Clifford Wolf	2014-08-16
\|
*	Fixed AOI/OAI expr handling in verilog backend	Clifford Wolf	2014-08-16
\|
*	Multiply using a carry-save accumulator	Clifford Wolf	2014-08-16
\|
*	Added "test_cell -s <seed>"	Clifford Wolf	2014-08-16
\|
*	AST ProcessGenerator: replaced subst__{from,to} with subst__map	Clifford Wolf	2014-08-16
\|
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16
\| \| \| \|	$_OAI4_
*	Added CellTypes::cell_evaluable()	Clifford Wolf	2014-08-16
\|
*	Changes in techmap $__alu interface	Clifford Wolf	2014-08-16
\|
*	Added "opt -fast"	Clifford Wolf	2014-08-16
\|
*	Added log_spacer()	Clifford Wolf	2014-08-16
\|
*	Bugfix in iopadmap	Clifford Wolf	2014-08-15
\|
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
\|
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15
\|
*	Removed old doc references to $safe_pmux	Clifford Wolf	2014-08-15
\|
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
\|
*	Added Frontend "+/" filename syntax for files from proc_share_dir	Clifford Wolf	2014-08-15
\|
*	document "techmap -map %<design-name>"	Clifford Wolf	2014-08-15
\|
*	Fixed bug in "read_verilog -ignore_redef"	Clifford Wolf	2014-08-15
\|
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14
\|
*	Changed the AST genWidthRTLIL subst interface to use a std::map	Clifford Wolf	2014-08-14
\|
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14
\|
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
\|
*	Fixed handling of task outputs	Clifford Wolf	2014-08-14
\|
*	Simplified $__arraymul techmap rule	Clifford Wolf	2014-08-14
\|
*	Added module->ports	Clifford Wolf	2014-08-14
\|
*	Refactoring of CellType class	Clifford Wolf	2014-08-14
\|
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
\|
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14
\|
*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14
\|
*	Updated ABC to 4935c2b946de	Clifford Wolf	2014-08-14
\|
*	Added techmap support for actual lookahead carry unit	Clifford Wolf	2014-08-13
\|
*	Preparations for lookahead ALU support in techmap.v	Clifford Wolf	2014-08-13
\|
*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13
\|
*	New interface for $__alu in techmap.v	Clifford Wolf	2014-08-13
\|
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
\|
*	Fixed handling of constant-true branches in proc_clean	Clifford Wolf	2014-08-12
\|
*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12
\|