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Age
*
Fixed "opt_const -fine" for $pos cells
Clifford Wolf
2014-09-04
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Removed $bu0 cell type
Clifford Wolf
2014-09-04
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Using $pos models for $bu0
Clifford Wolf
2014-09-03
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Fixed "test_cells -vlog"
Clifford Wolf
2014-09-03
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Fixes in $alu SAT- and eval-models
Clifford Wolf
2014-09-03
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Undef-related fixes in simlib $alu model
Clifford Wolf
2014-09-02
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Improvements in "test_cell -vlog"
Clifford Wolf
2014-09-02
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Added test_cell -vlog
Clifford Wolf
2014-09-02
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Create a default selection stack in RTLIL::Design::Design()
Clifford Wolf
2014-09-02
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Small bug fixes in $not, $neg, and $shiftx models
Clifford Wolf
2014-09-02
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Added SAT testing to test_cell eval stage
Clifford Wolf
2014-09-02
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Removed references to yosys-svgviewer from docs
Clifford Wolf
2014-09-02
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Removed yosys-svgviewer
Clifford Wolf
2014-09-02
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Using "xdot" instead of "yosys-svgviewer" in show command
Clifford Wolf
2014-09-02
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Added $alu support to test_cell
Clifford Wolf
2014-09-01
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Added ConstEval model for $alu cells
Clifford Wolf
2014-09-01
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Added SAT model for $alu cells
Clifford Wolf
2014-09-01
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Fixed "test_cell -simlib all"
Clifford Wolf
2014-09-01
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Added "test_cell -simlib -v"
Clifford Wolf
2014-09-01
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Added "techmap -autoproc"
Clifford Wolf
2014-09-01
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Fixes in old SAT example.ys
Clifford Wolf
2014-09-01
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Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
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Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵
Clifford Wolf
2014-09-01
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RTLIL::SigChunk::data
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Added eval testing to test_cell
Clifford Wolf
2014-08-31
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Fixed return size of const_*() eval functions
Clifford Wolf
2014-08-31
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Added RTLIL::Const::size()
Clifford Wolf
2014-08-31
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Added eval model for $lut cells
Clifford Wolf
2014-08-31
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Typo fixes in cell->*Param() API
Clifford Wolf
2014-08-31
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Added $lut support in test_cell, techmap, satgen
Clifford Wolf
2014-08-31
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Added design->scratchpad
Clifford Wolf
2014-08-30
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Added $alu cell type
Clifford Wolf
2014-08-30
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Added autotest -e (do not use -noexpr on write_verilog)
Clifford Wolf
2014-08-30
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Improved write address decoder generation memory_map
Clifford Wolf
2014-08-30
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Fixed module->addPmux()
Clifford Wolf
2014-08-30
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Using worker class in memory_map
Clifford Wolf
2014-08-30
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Replaced $__alu CO/CS outputs with full-width CO output
Clifford Wolf
2014-08-30
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Don't change existing binary FSM encoding if it is already optimal
Clifford Wolf
2014-08-30
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Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf
2014-08-30
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Improved handling of $pmux cells in fsm_extract
Clifford Wolf
2014-08-30
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Fixed inserting of Q-inverters in dfflibmap
Clifford Wolf
2014-08-27
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Fixed printing of multi-line Makefile.conf
Clifford Wolf
2014-08-27
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Implemented "rename -enumerate -pattern"
Clifford Wolf
2014-08-26
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Print Makefile.conf as make info message
Clifford Wolf
2014-08-26
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Checking for valid CONFIG value in Makefile
Clifford Wolf
2014-08-25
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Optimize shift ops with constant rhs in opt_const
Clifford Wolf
2014-08-24
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Added some additional log messages to opt_const
Clifford Wolf
2014-08-24
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Added is_signed argument to SigSpec.as_int() and Const.as_int()
Clifford Wolf
2014-08-24
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azonenberg: Make dump_vcd save model when temporal induction fails due to ↵
Clifford Wolf
2014-08-24
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step limit
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Only call proc_share_dirname() in techmap when necessary
Clifford Wolf
2014-08-23
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
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