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Commit message (
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Author
Age
*
separated memory next from write cell
Ahmed Irfan
2015-04-03
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Added ENABLE_NDEBUG makefile options
Clifford Wolf
2015-01-24
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namespace Yosys
Clifford Wolf
2014-09-27
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Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-09-22
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*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
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Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
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No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Use log_abort() and log_assert() in BTOR backend
Clifford Wolf
2014-03-07
*
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fixed memory next issue, when same memory is written in different case statement
ahmedirfan1983
2014-09-18
*
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added $pmux cell translation
Ahmed Irfan
2014-09-02
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/
*
register output corrected
Ahmed Irfan
2014-02-11
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added concat and slice cell translation
Ahmed Irfan
2014-02-11
*
Fixed gcc compiler warnings with release build
Clifford Wolf
2014-02-06
*
Added BTOR backend README file
Clifford Wolf
2014-02-05
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
*
root bug corrected
Ahmed Irfan
2014-01-25
*
removed regex include
Ahmed Irfan
2014-01-24
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merged clifford changes + removed regex
Ahmed Irfan
2014-01-24
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slice bug corrected
Ahmed Irfan
2014-01-20
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assert feature
Ahmed Irfan
2014-01-20
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verilog default options pull
Ahmed Irfan
2014-01-17
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slice error corrected
Ahmed Irfan
2014-01-16
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width issues
Ahmed Irfan
2014-01-15
*
BTOR backend
Ahmed Irfan
2014-01-14
*
btor
Ahmed Irfan
2014-01-03