index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
backends
/
spice
Commit message (
Expand
)
Author
Age
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Added "top" attribute to mark top module in hierarchy
Clifford Wolf
2013-11-24
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Silenced a gcc warning in spice backend
Clifford Wolf
2013-11-09
*
Write yosys version to output files
Clifford Wolf
2013-11-03
*
Fixed handling of boolean attributes (backends)
Clifford Wolf
2013-10-24
*
A couple of small fixes in SPICE backend
Clifford Wolf
2013-09-15
*
Added spice testbench to techlibs/cmos
Clifford Wolf
2013-09-14
*
Added spice backend
Clifford Wolf
2013-09-14