path: root/frontends/verilog/
Commit message (Expand)AuthorAge
* New upstream version 0.9Ruben Undheim2019-10-18
* New upstream version 0.7+20180830git0b7a184Ruben Undheim2018-08-30
* Fixed segfault on invalid verilog constant 1'b_Clifford Wolf2015-09-22
* Small corrections to const2ast warning messagesClifford Wolf2015-08-17
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-17
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-17
* Another block of spelling fixesLarry Doolittle2015-08-14
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-24
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-14
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-31
* Using log_assert() instead of assert()Clifford Wolf2014-07-28
* Improved parsing of large integer constantsClifford Wolf2014-06-15
* Fixed handling of unsized constants in verilog frontendClifford Wolf2014-01-24
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-09
* Added SAT generator and simple sat_solve commandClifford Wolf2013-06-07
* initial importClifford Wolf2013-01-05