Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Fixed two minor bugs in constant parsing | Clifford Wolf | 2014-11-24 |
* | Added warning for use of 'z' constants in HDL | Clifford Wolf | 2014-11-14 |
* | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 |
* | Using log_assert() instead of assert() | Clifford Wolf | 2014-07-28 |
* | Improved parsing of large integer constants | Clifford Wolf | 2014-06-15 |
* | Fixed handling of unsized constants in verilog frontend | Clifford Wolf | 2014-01-24 |
* | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 |
* | Added SAT generator and simple sat_solve command | Clifford Wolf | 2013-06-07 |
* | initial import | Clifford Wolf | 2013-01-05 |