Commit message (Expand) | Author | Age | |
---|---|---|---|
* | Fixed handling of unsized constants in verilog frontend | Clifford Wolf | 2014-01-24 |
* | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 |
* | Added SAT generator and simple sat_solve command | Clifford Wolf | 2013-06-07 |
* | initial import | Clifford Wolf | 2013-01-05 |