path: root/frontends/verilog/lexer.l
Commit message (Expand)AuthorAge
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-14
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-12
* added while and repeat support to verilog parserClifford Wolf2014-06-06
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-20
* Added support for `line compiler directiveClifford Wolf2014-03-11
* Added Verilog support for "`default_nettype none"Clifford Wolf2014-02-17
* Added Verilog parser support for assertsClifford Wolf2014-01-19
* Added proper === and !== support in constant expressionsClifford Wolf2013-12-27
* Enable {* .. *} feature per default (removes dependency to REJECT feature in ...Clifford Wolf2013-11-22
* Implemented indexed part selectsClifford Wolf2013-11-20
* Added "synthesis" in (synopsys|synthesis) comment supportClifford Wolf2013-11-20
* fixed Verilog parser filename and line numbering issue with include filesJohann Glaser2013-08-21
* Added support for notif0/notif1 primitivesJohann Glaser2013-08-20
* Added support for bufif0/bufif1 primitivesClifford Wolf2013-08-19
* Added defparam support to Verilog/AST frontendClifford Wolf2013-07-04
* More fixes for bugs found using xsthammerClifford Wolf2013-06-13
* Further improved and extended xsthammerClifford Wolf2013-06-11
* Added support for verilog === operatorClifford Wolf2013-05-07
* Improvements and bugfixes for generate blocks with local signalsClifford Wolf2013-03-26
* initial importClifford Wolf2013-01-05