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verilog
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Author
Age
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Fixed handling of parameters and localparams in functions
Clifford Wolf
2015-11-11
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Fixed bug in verilog parser
Clifford Wolf
2015-10-15
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SystemVerilog also has assume(), added implicit -D FORMAL
Clifford Wolf
2015-10-13
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Added support for "parameter" and "localparam" in global context
Clifford Wolf
2015-10-07
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Added read_verilog -nodpi
Clifford Wolf
2015-09-23
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Fixed support for $write system task
Clifford Wolf
2015-09-23
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Fixed detection of "task foo(bar);" syntax error
Clifford Wolf
2015-09-22
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Fixed segfault on invalid verilog constant 1'b_
Clifford Wolf
2015-09-22
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Small corrections to const2ast warning messages
Clifford Wolf
2015-08-17
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Check base-n literals only contain valid digits
Florian Zeitz
2015-08-17
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Warn on literals exceeding the specified bit width
Florian Zeitz
2015-08-17
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Another block of spelling fixes
Larry Doolittle
2015-08-14
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Smaller this time
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Re-created command-reference-manual.tex, copied some doc fixes to online help
Clifford Wolf
2015-08-14
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Adjust makefiles to work with out-of-tree builds
Clifford Wolf
2015-08-12
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This is based on work done by Larry Doolittle
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Fixed handling of [a-fxz?] in decimal constants
Clifford Wolf
2015-08-11
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Add -noautowire option to verilog frontend
Marcus Comstedt
2015-08-01
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Verilog front-end: define `BLACKBOX in -lib mode
Clifford Wolf
2015-04-19
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Ignore celldefine directive in verilog front-end
Clifford Wolf
2015-03-25
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Added non-std verilog assume() statement
Clifford Wolf
2015-02-26
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Parser support for complex delay expressions
Clifford Wolf
2015-02-20
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YosysJS stuff
Clifford Wolf
2015-02-19
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Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf
2015-02-14
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Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf
2015-02-14
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Improved read_verilog support for empty behavioral statements
Clifford Wolf
2015-02-10
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Ignoring more system task and functions
Clifford Wolf
2015-01-15
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Enable bison to be customized
Fabio Utzig
2015-01-08
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Define YOSYS and SYNTHESIS in preproc
Clifford Wolf
2015-01-02
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Improved some warning messages
Clifford Wolf
2014-12-27
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Fixed supply0/supply1 with many wires
Clifford Wolf
2014-12-11
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Fixed minor bug in parsing delays
Clifford Wolf
2014-11-24
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Fixed two minor bugs in constant parsing
Clifford Wolf
2014-11-24
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Added warning for use of 'z' constants in HDL
Clifford Wolf
2014-11-14
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Fixed parsing of nested verilog concatenation and replicate
Clifford Wolf
2014-11-12
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Added log_warning() API
Clifford Wolf
2014-11-09
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Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."
Clifford Wolf
2014-10-30
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Added support for task and function args in parentheses
Clifford Wolf
2014-10-27
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Re-introduced Yosys::readsome() helper function
Clifford Wolf
2014-10-23
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(f.read() + f.gcount() made problems with lines > 16kB)
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Print "SystemVerilog" in "read_verilog -sv" log messages
Clifford Wolf
2014-10-16
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Updated .gitignore file for ilang and verilog frontends
Clifford Wolf
2014-10-15
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Replaced readsome() with read() and gcount()
Clifford Wolf
2014-10-15
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Updated lexers & parsers to include prefixes
William Speirs
2014-10-15
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Fixed win32 troubles with f.readsome()
Clifford Wolf
2014-10-11
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Added format __attribute__ to stringf()
Clifford Wolf
2014-10-10
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
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Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
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Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
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Added support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf
2014-08-22
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