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* Squashed commit of the following:Ruben Undheim2016-09-23
* Added addBufGate module methodClifford Wolf2016-02-02
* rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)Rick Altherr2016-01-31
* rtlil: speed up SigSpec::sort_and_unify()Rick Altherr2016-01-31
* rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)Rick Altherr2016-01-31
* rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)Rick Altherr2016-01-31
* rtlil: rewrite remove2() to avoid copyingRick Altherr2016-01-30
* rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-29
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-25
* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-24
* Fixed driver conflict handling (various cmds)Clifford Wolf2015-10-24
* Fixed handling of driver-driver conflicts in wreduceClifford Wolf2015-10-24
* Added read-enable to memory modelClifford Wolf2015-09-25
* Cosmetic fix in Module::addLut()Clifford Wolf2015-09-18
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-16
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-11
* Added WORDS parameter to $meminitClifford Wolf2015-07-31
* Fixed trailing whitespacesClifford Wolf2015-07-02
* Added design->rename(module, new_name)Clifford Wolf2015-06-30
* Added "rename -top new_name"Clifford Wolf2015-06-17
* Fixed cstr_buf for std::string with small string optimizationClifford Wolf2015-06-11
* Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-08
* Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-29
* Improved attributes API and handling of "src" attributesClifford Wolf2015-04-24
* Avoid parameter values with size 0 ($mem cells)Clifford Wolf2015-04-05
* Added $_MUX4_, $_MUX8_, and $_MUX16_ cell typesClifford Wolf2015-04-05
* Added $assume cell typeClifford Wolf2015-02-26
* Added $meminit support to "memory" commandClifford Wolf2015-02-14
* Added $meminit cell typeClifford Wolf2015-02-14
* Added SigSpec::has_const()Clifford Wolf2015-02-08
* Added cell->known(), cell->input(portname), cell->output(portname)Clifford Wolf2015-02-07
* Skip blackbox modules in design->selected_modules()Clifford Wolf2015-02-03
* Added "equiv_make -blacklist <file> -encfile <file>"Clifford Wolf2015-01-31
* Added dict/pool.sort()Clifford Wolf2015-01-24
* Progress in equiv_simpleClifford Wolf2015-01-21
* Added equiv_make commandClifford Wolf2015-01-19
* Added $equiv cell typeClifford Wolf2015-01-19
* Optimizing no-op cell->setPort()Clifford Wolf2015-01-17
* Removed SigSpec::extend_xx() apiClifford Wolf2015-01-01
* added hashlib::mkhash_initClifford Wolf2014-12-30
* Added "yosys -X"Clifford Wolf2014-12-29
* Added mkhash_xorshift()Clifford Wolf2014-12-29
* Added memhasher (yosys -M)Clifford Wolf2014-12-28
* Fixed performance bug in object hashingClifford Wolf2014-12-28
* Renamed hashmap.h to hashlib.h, some related improvementsClifford Wolf2014-12-28
* More dict/pool related changesClifford Wolf2014-12-27
* More hashtable finetuningClifford Wolf2014-12-27
* Replaced std::unordered_set (nodict) with Yosys::poolClifford Wolf2014-12-26
* Replaced std::unordered_map as implementation for Yosys::dictClifford Wolf2014-12-26
* Added new_dict (hashmap.h) and re-enabled code coverage countersClifford Wolf2014-12-26