path: root/passes/abc/
Commit message (Expand)AuthorAge
* abc/blifparse files reorganizationClifford Wolf2015-05-17
* Added .barbuf support to abc BLIF parserClifford Wolf2015-05-13
* Less verbose ABC outputClifford Wolf2014-12-29
* namespace YosysClifford Wolf2014-09-27
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* Added module->portsClifford Wolf2014-08-14
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-31
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
* Use only module->addCell() and module->remove() to create and delete cellsClifford Wolf2014-07-25
* Removed RTLIL::SigSpec::optimize()Clifford Wolf2014-07-23
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-22
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-22
* Fixed memory corruption in passes/abc/blifparse.ccClifford Wolf2014-03-11
* Fixed use of limited length buffer in ABC blif parserClifford Wolf2013-12-31
* Added abc -dff and -clk supportClifford Wolf2013-12-31
* Always use BLIF as ABC output formatClifford Wolf2013-12-31
* Renamed temp module generated by "abc" pass from "logic" to "netlist"Clifford Wolf2013-11-19
* Fixed abc pass blif parser for constant bitsClifford Wolf2013-11-13
* Added $lut cells and abc lut mapping supportClifford Wolf2013-07-23