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Author
Age
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Renamed hashmap.h to hashlib.h, some related improvements
Clifford Wolf
2014-12-28
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More hashtable finetuning
Clifford Wolf
2014-12-27
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Replaced std::unordered_set (nodict) with Yosys::pool
Clifford Wolf
2014-12-26
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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namespace Yosys
Clifford Wolf
2014-09-27
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Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵
Clifford Wolf
2014-07-22
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created interim RTLIL::SigSpec::chunks_rw()
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
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Added delete {-input|-output|-port}
Clifford Wolf
2014-02-09
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Bugfix in delete command
Clifford Wolf
2014-02-09
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Added delete command
Clifford Wolf
2014-02-02