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Age
*
New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
*
Imported yosys 0.7
Ruben Undheim
2016-11-03
*
Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Added "int ceil_log2(int)" function
Clifford Wolf
2016-02-13
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Import more std:: stuff into Yosys namespace
Clifford Wolf
2015-10-25
*
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Clifford Wolf
2015-10-24
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Do not detect fsm state registers with init attribute
Clifford Wolf
2015-09-21
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Added $logic_not handling to fsm_detect
Clifford Wolf
2015-09-18
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Bugfix in fsm_detect for complex muxtrees
Clifford Wolf
2015-08-18
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Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
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Bugfix in fsm_extract
Clifford Wolf
2015-07-03
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added $eq/$neq -> $logic_not/$reduce_bool optimization
Clifford Wolf
2015-04-29
*
Added onehot attribute
Clifford Wolf
2015-02-04
*
Added "fsm -encfile"
Clifford Wolf
2015-01-30
*
Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Added log_warning() API
Clifford Wolf
2014-11-09
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Changed from "and" to "&&"
William Speirs
2014-10-15
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Do not the 'z' modifier in format string (another win32 fix)
Clifford Wolf
2014-10-11
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Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
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namespace Yosys
Clifford Wolf
2014-09-27
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Don't change existing binary FSM encoding if it is already optimal
Clifford Wolf
2014-08-30
*
Using $pmux info in fsm_extract to optimize transition ctrl_in patterns
Clifford Wolf
2014-08-30
*
Improved handling of $pmux cells in fsm_extract
Clifford Wolf
2014-08-30
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Added module->uniquify()
Clifford Wolf
2014-08-16
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More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
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RIP $safe_pmux
Clifford Wolf
2014-08-14
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Some improvements in FSM mapping and recoding
Clifford Wolf
2014-08-14
*
Fixed FSM mapping for multiple reset-like signals
Clifford Wolf
2014-08-10
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Some improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf
2014-08-09
*
Another fsm_extract bugfix
Clifford Wolf
2014-08-08
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Fixed "fsm -export"
Clifford Wolf
2014-08-08
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Fixed fsm_extract for wreduced muxes
Clifford Wolf
2014-08-08
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No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
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More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
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Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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Added log_cmd_error_expection
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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