yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Imported yosys 0.7	Ruben Undheim	2016-11-03
*	Squashed commit of the following:	Ruben Undheim	2016-09-23
*	Added "int ceil_log2(int)" function	Clifford Wolf	2016-02-13
*	Import more std:: stuff into Yosys namespace	Clifford Wolf	2015-10-25
*	renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()	Clifford Wolf	2015-10-24
*	Do not detect fsm state registers with init attribute	Clifford Wolf	2015-09-21
*	Added $logic_not handling to fsm_detect	Clifford Wolf	2015-09-18
*	Bugfix in fsm_detect for complex muxtrees	Clifford Wolf	2015-08-18
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Bugfix in fsm_extract	Clifford Wolf	2015-07-03
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Added $eq/$neq -> $logic_not/$reduce_bool optimization	Clifford Wolf	2015-04-29
*	Added onehot attribute	Clifford Wolf	2015-02-04
*	Added "fsm -encfile"	Clifford Wolf	2015-01-30
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	Changed from "and" to "&&"	William Speirs	2014-10-15
*	Do not the 'z' modifier in format string (another win32 fix)	Clifford Wolf	2014-10-11
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Corrected spelling mistakes found by lintian	Ruben Undheim	2014-09-06
*	Don't change existing binary FSM encoding if it is already optimal	Clifford Wolf	2014-08-30
*	Using $pmux info in fsm_extract to optimize transition ctrl_in patterns	Clifford Wolf	2014-08-30
*	Improved handling of $pmux cells in fsm_extract	Clifford Wolf	2014-08-30
*	Added module->uniquify()	Clifford Wolf	2014-08-16
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15
*	RIP $safe_pmux	Clifford Wolf	2014-08-14
*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14
*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10
*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09
*	Another fsm_extract bugfix	Clifford Wolf	2014-08-08
*	Fixed "fsm -export"	Clifford Wolf	2014-08-08
*	Fixed fsm_extract for wreduced muxes	Clifford Wolf	2014-08-08
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28
*	Added log_cmd_error_expection	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27
*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26
*	Added RTLIL::Cell::has(portname)	Clifford Wolf	2014-07-26
*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25
*	Various small fixes (from gcc compiler warnings)	Clifford Wolf	2014-07-23