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proc
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proc_arst.cc
Commit message (
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Author
Age
*
Removed SigSpec::extend_xx() api
Clifford Wolf
2015-01-01
*
Renamed extend() to extend_xx(), changed most users to extend_u0()
Clifford Wolf
2014-12-24
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
Clifford Wolf
2014-02-21
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
*
Added "proc_arst -global_arst" feature
Clifford Wolf
2013-11-20
*
Added handling of multiple async paths in proc_arst
Clifford Wolf
2013-10-19
*
Added nosync attribute and some async reset related fixes
Clifford Wolf
2013-03-25
*
Added help messages to proc_* passes
Clifford Wolf
2013-03-01
*
initial import
Clifford Wolf
2013-01-05