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sat
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Author
Age
*
Added "sat -prove-skip"
Clifford Wolf
2014-08-08
*
Use "-keepdc" in "miter -equiv -flatten"
Clifford Wolf
2014-08-07
*
Fixed "share" for memory read ports
Clifford Wolf
2014-08-03
*
Removed at() method from RTLIL::IdString
Clifford Wolf
2014-08-02
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Renamed modwalker.h to modtools.h
Clifford Wolf
2014-07-31
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3
Clifford Wolf
2014-07-23
*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Removed deprecated module->new_wire()
Clifford Wolf
2014-07-21
*
Wider range of cell types supported in "share" pass
Clifford Wolf
2014-07-21
*
Use ezSAT::non_incremental() in "share" pass
Clifford Wolf
2014-07-21
*
Added support for resource sharing in mux control logic
Clifford Wolf
2014-07-20
*
Supercell creation for $div/$mod worked all along, fixed test benches
Clifford Wolf
2014-07-20
*
Fixed creation of shift supercells in "share" pass
Clifford Wolf
2014-07-20
*
Added "miter -equiv -flatten"
Clifford Wolf
2014-07-20
*
Added "share" supercell creation
Clifford Wolf
2014-07-20
*
Added removing of always inactive cells to "share" pass
Clifford Wolf
2014-07-20
*
Progress in "share" pass
Clifford Wolf
2014-07-20
*
Progress in "share" pass
Clifford Wolf
2014-07-20
*
Started to implement real resource sharing
Clifford Wolf
2014-07-19
*
now ignore init attributes on non-register wires in sat command
Clifford Wolf
2014-07-05
*
added log_header to miter and expose pass, show cell type for exposed ports
Johann Glaser
2014-05-28
*
Small improvement in SAT log messages
Clifford Wolf
2014-03-13
*
Fixed bug in freduce command
Clifford Wolf
2014-03-07
*
Some minor code cleanups in freduce command
Clifford Wolf
2014-03-07
*
Added freduce -dump
Clifford Wolf
2014-03-06
*
Added freduce -stop
Clifford Wolf
2014-03-06
*
fixed freduce for Minisat::SimpSolver: use frozen_literal()
Clifford Wolf
2014-03-03
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