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path: root/passes/techmap/Makefile.inc
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* Added nlutmapClifford Wolf2015-09-18
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* Added lut2mux passClifford Wolf2015-09-18
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* Added tribuf commandClifford Wolf2015-08-16
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* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-12
| | | | This is based on work done by Larry Doolittle
* Renamed "aig" to "aigmap"Clifford Wolf2015-06-10
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* Added "aig" passClifford Wolf2015-06-09
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* abc/blifparse files reorganizationClifford Wolf2015-05-17
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* Added "pmuxtree" commandClifford Wolf2015-04-07
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* Added "muxcover" commandClifford Wolf2015-04-07
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* Added "dffinit", Support for initialized Xilinx DFFClifford Wolf2015-04-04
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* More emscripten stuff, Added example appClifford Wolf2015-02-15
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* Fixed build with SMALL=1Clifford Wolf2014-12-30
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* Added skeleton dff2dffe passClifford Wolf2014-12-08
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* Added genfiles.zip to MXE "make dist"Clifford Wolf2014-10-17
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* Added mxe-based cross build for win32Clifford Wolf2014-10-09
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* alumacc skeletonClifford Wolf2014-09-14
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* Added "maccmap" commandClifford Wolf2014-09-07
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* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-31
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* Added "make SMALL=1"Clifford Wolf2014-07-24
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* Added "make PRETTY=1"Clifford Wolf2014-07-24
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* OSX compatible creation of stdcells.inc, using code from ↵Clifford Wolf2014-03-11
| | | | | | github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
* Moved some passes to other source directoriesClifford Wolf2014-02-08
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* Added hilomap commandClifford Wolf2014-01-19
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* Added simplemap passClifford Wolf2013-11-24
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* Added iopadmap passClifford Wolf2013-10-16
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* Moved dfflibmap from passes/dfflibmap to passes/techmapClifford Wolf2013-10-16
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15
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* Removed date from auto-generated passes/techmap/stdcells.incClifford Wolf2013-03-18
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* add header to autogenerated file on its originJohann Glaser2013-03-18
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* initial importClifford Wolf2013-01-05