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extract.cc
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Author
Age
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
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Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
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Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
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Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵
Clifford Wolf
2014-07-22
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created interim RTLIL::SigSpec::chunks_rw()
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Added "extract -ignore_parameters" and "extract -ignore_param ..."
Clifford Wolf
2014-02-20
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Added "extract -map %<design_name>"
Clifford Wolf
2014-02-20
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Moved some passes to other source directories
Clifford Wolf
2014-02-08