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*
Added support for $clog2 system function
Clifford Wolf
2013-12-04
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*
Various improvements in support for generate statements
Clifford Wolf
2013-12-04
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*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
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*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
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*
Added support for local regs in named blocks
Clifford Wolf
2013-12-04
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*
Fixed temp net name generation in rtlil process generator for abbreviated ↵
Clifford Wolf
2013-11-28
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name matching
*
Added "src" attribute to processes
Clifford Wolf
2013-11-28
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*
Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
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*
Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
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*
Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
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*
Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
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*
Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
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*
Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
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*
Improved handling of initialized registers
Clifford Wolf
2013-11-23
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*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
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*
Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf
2013-11-22
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*
Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵
Clifford Wolf
2013-11-22
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flex)
*
Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
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*
Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
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*
Fixed ilang parser: memory width
Clifford Wolf
2013-11-20
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*
Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
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*
Implemented indexed part selects
Clifford Wolf
2013-11-20
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*
Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
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*
Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf
2013-11-20
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*
Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
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*
Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
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*
Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
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*
Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
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*
Fixed two bugs in mem2reg functionality in AST frontend
Clifford Wolf
2013-11-18
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*
Added dumping of attributes in AST frontend
Clifford Wolf
2013-11-18
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*
Fixed parsing of default cases when not last case
Clifford Wolf
2013-11-18
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*
Fixed mem2reg for reg usage outside always block
Clifford Wolf
2013-11-18
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*
Fixed parsing of "parameter integer"
Clifford Wolf
2013-11-13
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*
Cleanups and bugfixes in response to new internal cell checker
Clifford Wolf
2013-11-11
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*
Call internal checker more often
Clifford Wolf
2013-11-10
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*
More undef-propagation related fixes
Clifford Wolf
2013-11-08
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*
Fixed handling of different signedness in power operands
Clifford Wolf
2013-11-08
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*
Implemented const folding of ternary op with undef select
Clifford Wolf
2013-11-08
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*
Fixed handling of power operator
Clifford Wolf
2013-11-07
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*
Fixed more extend vs. extend_u0 issues
Clifford Wolf
2013-11-07
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*
Disabled const folding of ternary op when select is undef
Clifford Wolf
2013-11-07
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*
Renamed extend_un0() to extend_u0() and use it in genrtlil
Clifford Wolf
2013-11-07
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*
Fixed sign handling in constants
Clifford Wolf
2013-11-07
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*
Fixed const folding in corner cases with parameters
Clifford Wolf
2013-11-07
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*
Fixed width detection for replicate operator
Clifford Wolf
2013-11-07
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*
Fixed at_zero evaluation of dynamic ranges
Clifford Wolf
2013-11-07
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*
Various fixes for correct parameter support
Clifford Wolf
2013-11-07
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*
Fixed the fix for propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-07
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*
Fixed propagation of width hints for $signed() and $unsigned()
Clifford Wolf
2013-11-06
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*
Additional fixes for undef propagation in concat and replicate ops
Clifford Wolf
2013-11-06
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