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rename.cc
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Author
Age
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added design->rename(module, new_name)
Clifford Wolf
2015-06-30
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Added "rename -top new_name"
Clifford Wolf
2015-06-17
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Fixed iterator invalidation bug in "rename" command
Clifford Wolf
2015-02-09
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Added Yosys::{dict,nodict,vector} container types
Clifford Wolf
2014-12-26
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Added missing fixup_ports() calls to "rename" command
Clifford Wolf
2014-11-08
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namespace Yosys
Clifford Wolf
2014-09-27
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Implemented "rename -enumerate -pattern"
Clifford Wolf
2014-08-26
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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Changed more code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
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Added "rename -hide" command
Clifford Wolf
2014-01-02
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Improved handling of private names in opt_clean and rename commands
Clifford Wolf
2013-08-07
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Added renaming of wires and cells to "rename" command
Clifford Wolf
2013-06-19
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Added "rename" command
Clifford Wolf
2013-06-10