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Author
Age
*
Added support for "keep" on modules
Clifford Wolf
2014-09-29
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Re-enabled assert for new logic loops in "share" pass
Clifford Wolf
2014-09-21
*
Various improvements regarding logic loops in "share" results
Clifford Wolf
2014-09-21
*
Logic loop bugfix for "share" pass
Clifford Wolf
2014-09-21
*
Added "share -limit"
Clifford Wolf
2014-09-21
*
Still loop bug in "share": changed assert to warning
Clifford Wolf
2014-09-21
*
Do not introduce new logic loops in "share"
Clifford Wolf
2014-09-21
*
Assert on new logic loops in "share" pass
Clifford Wolf
2014-09-21
*
Fixed wreduce $shiftx handling
Clifford Wolf
2014-09-15
*
Cleanup in wreduce
Clifford Wolf
2014-09-14
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
*
Fixed "opt_const -fine" for $pos cells
Clifford Wolf
2014-09-04
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
*
Moved "share" and "wreduce" to passes/opt/
Clifford Wolf
2014-09-01
*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
*
Added design->scratchpad
Clifford Wolf
2014-08-30
*
Optimize shift ops with constant rhs in opt_const
Clifford Wolf
2014-08-24
*
Added some additional log messages to opt_const
Clifford Wolf
2014-08-24
*
Renamed toposort.h to utils.h
Clifford Wolf
2014-08-17
*
Added "opt -fast"
Clifford Wolf
2014-08-16
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
*
More idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf
2014-08-15
*
RIP $safe_pmux
Clifford Wolf
2014-08-14
*
Fixed a performance bug in opt_reduce
Clifford Wolf
2014-08-02
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
*
Added SigPool::check(bit)
Clifford Wolf
2014-07-27
*
Fixed bug in opt_clean
Clifford Wolf
2014-07-27
*
Improved performance of opt_const on large modules
Clifford Wolf
2014-07-27
*
Fixed a bug in opt_clean and some RTLIL API usage cleanups
Clifford Wolf
2014-07-27
*
Using new obj iterator API in a few places
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Fixed memory corruption in "opt_reduce" pass
Clifford Wolf
2014-07-25
*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
*
Added cover() calls to opt_const
Clifford Wolf
2014-07-24
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
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