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* Added "maccmap" commandClifford Wolf2014-09-07
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* Added "test_cell -nosat"Clifford Wolf2014-09-07
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* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
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* Added $macc SAT modelClifford Wolf2014-09-06
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* Added $macc cell typeClifford Wolf2014-09-06
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2014-09-06
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| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
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* | Added "test_cell -script"Clifford Wolf2014-09-06
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* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
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* Removed $bu0 cell typeClifford Wolf2014-09-04
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* Fixed "test_cells -vlog"Clifford Wolf2014-09-03
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* Improvements in "test_cell -vlog"Clifford Wolf2014-09-02
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* Added test_cell -vlogClifford Wolf2014-09-02
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* Added SAT testing to test_cell eval stageClifford Wolf2014-09-02
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* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
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* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
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* Added $alu support to test_cellClifford Wolf2014-09-01
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* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
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* Added "techmap -autoproc"Clifford Wolf2014-09-01
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* Fixes in old SAT example.ysClifford Wolf2014-09-01
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* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
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* Using std::vector<RTLIL::State> instead of RTLIL::Const for ↵Clifford Wolf2014-09-01
| | | | RTLIL::SigChunk::data
* Added eval testing to test_cellClifford Wolf2014-08-31
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* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
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* Added design->scratchpadClifford Wolf2014-08-30
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* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
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* Using worker class in memory_mapClifford Wolf2014-08-30
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* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
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* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30
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* Improved handling of $pmux cells in fsm_extractClifford Wolf2014-08-30
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* Fixed inserting of Q-inverters in dfflibmapClifford Wolf2014-08-27
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* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-26
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* Optimize shift ops with constant rhs in opt_constClifford Wolf2014-08-24
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* Added some additional log messages to opt_constClifford Wolf2014-08-24
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* azonenberg: Make dump_vcd save model when temporal induction fails due to ↵Clifford Wolf2014-08-24
| | | | step limit
* Only call proc_share_dirname() in techmap when necessaryClifford Wolf2014-08-23
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-23
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* Changed backend-api from FILE to std::ostreamClifford Wolf2014-08-23
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* Added "stat -width"Clifford Wolf2014-08-22
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-22
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* Added "plugin" commandClifford Wolf2014-08-22
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* Renamed toposort.h to utils.hClifford Wolf2014-08-17
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* Added module->uniquify()Clifford Wolf2014-08-16
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* Added "test_cell -s <seed>"Clifford Wolf2014-08-16
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-16
| | | | $_OAI4_
* Added "opt -fast"Clifford Wolf2014-08-16
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* Bugfix in iopadmapClifford Wolf2014-08-15
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* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-15
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* More idstring sort_by_* helpers and fixed tpl ordering in techmapClifford Wolf2014-08-15
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