path: root/passes
Commit message (Expand)AuthorAge
* Added "abc -fast"Clifford Wolf2014-09-18
* Fixed $_NOR vs. $_NOR_ typo in abc.ccClifford Wolf2014-09-16
* Fixed $memwr/$memrd order in memory_dffClifford Wolf2014-09-16
* More aggressive $macc merging in alumaccClifford Wolf2014-09-15
* Added the obvious optimizations to alumacc $macc generatorClifford Wolf2014-09-15
* Improved maccmap tree bit packingClifford Wolf2014-09-15
* Fixed wreduce $shiftx handlingClifford Wolf2014-09-15
* Fixed techmap_wrap for techmap_celltypeClifford Wolf2014-09-14
* Various fixes/cleanups in alumacc and maccmapClifford Wolf2014-09-14
* Added techmap_wrap attributeClifford Wolf2014-09-14
* alumacc fix for $pos cellsClifford Wolf2014-09-14
* Extract $alu cells in alumaccClifford Wolf2014-09-14
* Merge $macc cells in alumacc passClifford Wolf2014-09-14
* Basic $macc extract in alumaccClifford Wolf2014-09-14
* alumacc skeletonClifford Wolf2014-09-14
* Cleanup in wreduceClifford Wolf2014-09-14
* Added $lcu cell typeClifford Wolf2014-09-08
* Added "$fa" cell typeClifford Wolf2014-09-08
* Trim msb/lsb zero bits from full adder in maccmapClifford Wolf2014-09-08
* Added "test_cell -const"Clifford Wolf2014-09-08
* Added 'techmap_maccmap' techmap attributeClifford Wolf2014-09-07
* Added "maccmap" commandClifford Wolf2014-09-07
* Added "test_cell -nosat"Clifford Wolf2014-09-07
* Various bug fixes (related to $macc model testing)Clifford Wolf2014-09-06
* Added $macc SAT modelClifford Wolf2014-09-06
* Added $macc cell typeClifford Wolf2014-09-06
* Merge branch 'master' of Wolf2014-09-06
| * Corrected spelling mistakes found by lintianRuben Undheim2014-09-06
* | Added "test_cell -script"Clifford Wolf2014-09-06
* Fixed "opt_const -fine" for $pos cellsClifford Wolf2014-09-04
* Removed $bu0 cell typeClifford Wolf2014-09-04
* Fixed "test_cells -vlog"Clifford Wolf2014-09-03
* Improvements in "test_cell -vlog"Clifford Wolf2014-09-02
* Added test_cell -vlogClifford Wolf2014-09-02
* Added SAT testing to test_cell eval stageClifford Wolf2014-09-02
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-02
* Using "xdot" instead of "yosys-svgviewer" in show commandClifford Wolf2014-09-02
* Added $alu support to test_cellClifford Wolf2014-09-01
* Added "test_cell -simlib -v"Clifford Wolf2014-09-01
* Added "techmap -autoproc"Clifford Wolf2014-09-01
* Fixes in old SAT example.ysClifford Wolf2014-09-01
* Moved "share" and "wreduce" to passes/opt/Clifford Wolf2014-09-01
* Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...Clifford Wolf2014-09-01
* Added eval testing to test_cellClifford Wolf2014-08-31
* Added $lut support in test_cell, techmap, satgenClifford Wolf2014-08-31
* Added design->scratchpadClifford Wolf2014-08-30
* Improved write address decoder generation memory_mapClifford Wolf2014-08-30
* Using worker class in memory_mapClifford Wolf2014-08-30
* Don't change existing binary FSM encoding if it is already optimalClifford Wolf2014-08-30
* Using $pmux info in fsm_extract to optimize transition ctrl_in patternsClifford Wolf2014-08-30