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*
Added spice testbench to techlibs/cmos
Clifford Wolf
2013-09-14
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Added spice backend
Clifford Wolf
2013-09-14
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Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos)
Clifford Wolf
2013-08-27
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Added simple xilinx7 technology mapping files
Clifford Wolf
2013-08-22
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Implemented same div-by-zero behavior as found in other synthesis tools
Clifford Wolf
2013-08-15
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Added $div and $mod technology mapping
Clifford Wolf
2013-08-09
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Added $lut cells and abc lut mapping support
Clifford Wolf
2013-07-23
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Fixed shift ops with large right hand side
Clifford Wolf
2013-07-09
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More fixes for bugs found using xsthammer
Clifford Wolf
2013-06-13
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More sign-extension related fixes
Clifford Wolf
2013-06-10
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Implemented technology mapping for multipliers (using array multiplier)
Clifford Wolf
2013-06-03
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Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
Clifford Wolf
2013-04-07
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Added EXTRA_TARGETS Makefile variable
Clifford Wolf
2013-03-28
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Tiny bugfix in simlib.v
Clifford Wolf
2013-03-26
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Fixed stdcells.v for $adff with undef reset value
Clifford Wolf
2013-03-24
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More support code for $sr cells
Clifford Wolf
2013-03-14
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added .gitignore files
Clifford Wolf
2013-01-05
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*
initial import
Clifford Wolf
2013-01-05
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