yosys - Debian dgit repo for package yosys

	Commit message (Expand)	Author	Age
*	Small corrections to const2ast warning messages	Clifford Wolf	2015-08-17
*	Check base-n literals only contain valid digits	Florian Zeitz	2015-08-17
*	Warn on literals exceeding the specified bit width	Florian Zeitz	2015-08-17
*	Another block of spelling fixes	Larry Doolittle	2015-08-14
*	Re-created command-reference-manual.tex, copied some doc fixes to online help	Clifford Wolf	2015-08-14
*	Spell check (by Larry Doolittle)	Clifford Wolf	2015-08-14
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
*	Fixed handling of [a-fxz?] in decimal constants	Clifford Wolf	2015-08-11
*	Add -noautowire option to verilog frontend	Marcus Comstedt	2015-08-01
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
*	Verilog front-end: define `BLACKBOX in -lib mode	Clifford Wolf	2015-04-19
*	Ignore celldefine directive in verilog front-end	Clifford Wolf	2015-03-25
*	Added non-std verilog assume() statement	Clifford Wolf	2015-02-26
*	Parser support for complex delay expressions	Clifford Wolf	2015-02-20
*	YosysJS stuff	Clifford Wolf	2015-02-19
*	Added "read_verilog -nomeminit" and "nomeminit" attribute	Clifford Wolf	2015-02-14
*	Fixed handling of "//" in filenames in verilog pre-processor	Clifford Wolf	2015-02-14
*	Improved read_verilog support for empty behavioral statements	Clifford Wolf	2015-02-10
*	Ignoring more system task and functions	Clifford Wolf	2015-01-15
*	Enable bison to be customized	Fabio Utzig	2015-01-08
*	Define YOSYS and SYNTHESIS in preproc	Clifford Wolf	2015-01-02
*	Improved some warning messages	Clifford Wolf	2014-12-27
*	Fixed supply0/supply1 with many wires	Clifford Wolf	2014-12-11
*	Fixed minor bug in parsing delays	Clifford Wolf	2014-11-24
*	Fixed two minor bugs in constant parsing	Clifford Wolf	2014-11-24
*	Added warning for use of 'z' constants in HDL	Clifford Wolf	2014-11-14
*	Fixed parsing of nested verilog concatenation and replicate	Clifford Wolf	2014-11-12
*	Added log_warning() API	Clifford Wolf	2014-11-09
*	Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."	Clifford Wolf	2014-10-30
*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27
*	Re-introduced Yosys::readsome() helper function	Clifford Wolf	2014-10-23
*	Print "SystemVerilog" in "read_verilog -sv" log messages	Clifford Wolf	2014-10-16
*	Updated .gitignore file for ilang and verilog frontends	Clifford Wolf	2014-10-15
*	Replaced readsome() with read() and gcount()	Clifford Wolf	2014-10-15
*	Updated lexers & parsers to include prefixes	William Speirs	2014-10-15
*	Fixed win32 troubles with f.readsome()	Clifford Wolf	2014-10-11
*	Added format __attribute__ to stringf()	Clifford Wolf	2014-10-10
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10
*	namespace Yosys	Clifford Wolf	2014-09-27
*	Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore	Clifford Wolf	2014-08-23
*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23
*	Added support for non-standard <plugin>:<c_name> DPI syntax	Clifford Wolf	2014-08-22
*	Added support for DPI function with different names in C and Verilog	Clifford Wolf	2014-08-21
*	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	Clifford Wolf	2014-08-21
*	Added support for global tasks and functions	Clifford Wolf	2014-08-21
*	Added "via_celltype" attribute on task/func	Clifford Wolf	2014-08-18
*	Fixed line numbers when using here-doc macros	Clifford Wolf	2014-08-14
*	Added support for non-standard """ macro bodies	Clifford Wolf	2014-08-13
*	Also allow "module foobar(input foo, output bar, ...);" syntax	Clifford Wolf	2014-08-07
*	Added AST_MULTIRANGE (arrays with more than 1 dimension)	Clifford Wolf	2014-08-06