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Author
Age
*
Bugfix in name resolution with generate blocks
Clifford Wolf
2014-01-30
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Added read_verilog -icells option
Clifford Wolf
2014-01-29
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Fixed handling of unsized constants in verilog frontend
Clifford Wolf
2014-01-24
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Fixed algorithmic complexity of AST simplification of long expressions
Clifford Wolf
2014-01-20
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Added $assert cell
Clifford Wolf
2014-01-19
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Added Verilog parser support for asserts
Clifford Wolf
2014-01-19
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Fixed parsing of verilog macros at end of line
Clifford Wolf
2014-01-18
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Added verilog_defaults command
Clifford Wolf
2014-01-17
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Fixed typo in frontends/ast/simplify.cc
Clifford Wolf
2014-01-12
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Added updating of RTLIL::autoidx to ilang frontend
Clifford Wolf
2014-01-03
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Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
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Fixed a stupid access after delete bug
Clifford Wolf
2013-12-29
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Fixed parsing of non-arg macro calls followed by "("
Clifford Wolf
2013-12-27
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Fixed parsing of macros with no arguments and expansion text starting with "("
Clifford Wolf
2013-12-27
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Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
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Added proper === and !== support in constant expressions
Clifford Wolf
2013-12-27
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Added elsif preproc support
Clifford Wolf
2013-12-18
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Added support for macro arguments
Clifford Wolf
2013-12-18
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Keep strings as strings in const ternary and concat
Clifford Wolf
2013-12-05
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Added const folding support for $signed and $unsigned
Clifford Wolf
2013-12-05
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Added AstNode::mkconst_str API
Clifford Wolf
2013-12-05
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Fixed generate-for (and disabled double warning for auto-wire)
Clifford Wolf
2013-12-04
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Added support for $clog2 system function
Clifford Wolf
2013-12-04
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Various improvements in support for generate statements
Clifford Wolf
2013-12-04
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Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
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Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
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Added support for local regs in named blocks
Clifford Wolf
2013-12-04
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Fixed temp net name generation in rtlil process generator for abbreviated ↵
Clifford Wolf
2013-11-28
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name matching
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Added "src" attribute to processes
Clifford Wolf
2013-11-28
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Added module->avail_parameters (for advanced techmap features)
Clifford Wolf
2013-11-24
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Added verilog frontend -ignore_redef option
Clifford Wolf
2013-11-24
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Early wire/reg/parameter width calculation in ast/simplify
Clifford Wolf
2013-11-24
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Added support for signed parameters in ilang
Clifford Wolf
2013-11-24
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Remove auto_wire framework (smarter than the verilog standard)
Clifford Wolf
2013-11-24
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Implemented correct handling of signed module parameters
Clifford Wolf
2013-11-24
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Improved handling of initialized registers
Clifford Wolf
2013-11-23
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Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
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Fixed O(n^2) performance bug in verilog preprocessor
Clifford Wolf
2013-11-22
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Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵
Clifford Wolf
2013-11-22
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flex)
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Fixed async proc detection in mem2reg
Clifford Wolf
2013-11-21
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Major improvements in mem2reg and added "init" sync rules
Clifford Wolf
2013-11-21
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Fixed ilang parser: memory width
Clifford Wolf
2013-11-20
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Another name resolution bugfix for generate blocks
Clifford Wolf
2013-11-20
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Implemented indexed part selects
Clifford Wolf
2013-11-20
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Do not allow memory bit select on the left side of an assignment
Clifford Wolf
2013-11-20
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Added "synthesis" in (synopsys|synthesis) comment support
Clifford Wolf
2013-11-20
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Fixed name resolution of local tasks and functions in generate block
Clifford Wolf
2013-11-20
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Implemented part/bit select on memory read
Clifford Wolf
2013-11-20
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Added init= attribute for fpga-style reset values
Clifford Wolf
2013-11-20
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Fixed parsing of module arguments when one type is used for many args
Clifford Wolf
2013-11-19
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