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path:
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/
passes
/
abc
/
blifparse.cc
Commit message (
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Author
Age
*
Less verbose ABC output
Clifford Wolf
2014-12-29
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
*
Added module->ports
Clifford Wolf
2014-08-14
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
*
Fixed memory corruption in passes/abc/blifparse.cc
Clifford Wolf
2014-03-11
*
Fixed use of limited length buffer in ABC blif parser
Clifford Wolf
2013-12-31
*
Added abc -dff and -clk support
Clifford Wolf
2013-12-31
*
Always use BLIF as ABC output format
Clifford Wolf
2013-12-31
*
Renamed temp module generated by "abc" pass from "logic" to "netlist"
Clifford Wolf
2013-11-19
*
Fixed abc pass blif parser for constant bits
Clifford Wolf
2013-11-13
*
Added $lut cells and abc lut mapping support
Clifford Wolf
2013-07-23