summaryrefslogtreecommitdiff
path: root/passes/cmds/add.cc
Commit message (Collapse)AuthorAge
* namespace YosysClifford Wolf2014-09-27
|
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-31
|
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-27
|
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-27
|
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-27
|
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-26
|
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-26
|
* Manual fixes for new cell connections APIClifford Wolf2014-07-26
|
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-26
| | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;'
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-26
|
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-22
|
* Fixed a bug in "add -global_input"Clifford Wolf2013-11-21
|
* Added "add" command (only wires for now)Clifford Wolf2013-11-20