path: root/techlibs/common/simlib.v
Commit message (Expand)AuthorAge
* Small bug fixes in $not, $neg, and $shiftx modelsClifford Wolf2014-09-02
* Fixed "test_cell -simlib all"Clifford Wolf2014-09-01
* Added $alu cell typeClifford Wolf2014-08-30
* Renamed $lut ports to follow A-Y naming schemeClifford Wolf2014-08-15
* RIP $safe_pmuxClifford Wolf2014-08-14
* Bugfix in simlib.v for iverilogClifford Wolf2014-07-29
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-29
* Fixed simlib.v model for $memClifford Wolf2014-07-17
* Updated simlib to new $mem/$memwr interfaceClifford Wolf2014-07-16
* Added SIMLIB_NOLUT to simlib.vClifford Wolf2014-04-02
* Added SIMLIB_NOSR to simlib.vClifford Wolf2014-04-02
* Added support for dlatchsr cellsClifford Wolf2014-03-31
* Added $slice and $concat cell typesClifford Wolf2014-02-07
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-03
* More changes to techlibs/common/simlib.v for LECClifford Wolf2014-01-31
* Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal)Clifford Wolf2014-01-29
* Added $assert cellClifford Wolf2014-01-19
* Fixed $lut simlib model for a wider range of toolsClifford Wolf2014-01-18
* More changes to simlib to make it friendlier to a wider range of toolsClifford Wolf2014-01-18
* Fixed a type in $mem model in simlib.vClifford Wolf2014-01-18
* Added $bu0 cell to simlib.vClifford Wolf2014-01-18
* Added support for non-const === and !== (for miter circuits)Clifford Wolf2013-12-27
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-24
* Cleanups and bugfixes in response to new internal cell checkerClifford Wolf2013-11-11
* Added $sr, $dffsr and $dlatch cell typesClifford Wolf2013-10-18
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-15