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synth_xilinx.cc
Commit message (
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Author
Age
*
New upstream version 0.9
Ruben Undheim
2019-10-18
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Imported GIT HEAD: 0.8+20190328git32bd0f2
Ruben Undheim
2019-03-28
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New upstream version 0.7+20180830git0b7a184
Ruben Undheim
2018-08-30
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Squashed commit of the following:
Ruben Undheim
2016-09-23
*
Run dffsr2dff in synth_xilinx
Clifford Wolf
2016-02-13
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Added "abc -luts" option, Improved Xilinx logic mapping
Clifford Wolf
2016-02-01
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Bugfix in Xilinx LUT mapping
Clifford Wolf
2015-10-30
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Added read-enable to memory model
Clifford Wolf
2015-09-25
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Fixed trailing whitespaces
Clifford Wolf
2015-07-02
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Added output args to synth_ice40
Clifford Wolf
2015-05-26
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Towards DRAM support in Xilinx flow
Clifford Wolf
2015-04-09
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Added Xilinx bram black-box modules
Clifford Wolf
2015-04-06
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Added "dffinit", Support for initialized Xilinx DFF
Clifford Wolf
2015-04-04
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Added "stat" to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
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Added final checks to "synth" and "synth_xilinx"
Clifford Wolf
2015-02-15
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no support for 6-series xilinx devices
Clifford Wolf
2015-02-01
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Added Xilinx example for Basys3 board
Clifford Wolf
2015-02-01
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Various cleanups in xilinx techlib
Clifford Wolf
2015-01-18
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Added synth_xilinx -retime -flatten
Clifford Wolf
2015-01-17
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Added MUXCY and XORCY support to synth_xilinx
Clifford Wolf
2015-01-17
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Added dff2dffe to synth_xilinx
Clifford Wolf
2015-01-16
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Added Xilinx MUXF7 and MUXF8 support
Clifford Wolf
2015-01-15
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Various cleanups in synth_xilinx command
Clifford Wolf
2015-01-13
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Various small improvements to synth_xilinx
Clifford Wolf
2015-01-06
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Towards Xilinx bram support
Clifford Wolf
2015-01-05
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namespace Yosys
Clifford Wolf
2014-09-27
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Added "techmap -share_map" option
Clifford Wolf
2013-11-24
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Added synth_xilinx command
Clifford Wolf
2013-10-27