index
:
yosys
master
Debian dgit repo for package yosys
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
backends
/
verilog
Commit message (
Expand
)
Author
Age
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
*
Added support for non-const === and !== (for miter circuits)
Clifford Wolf
2013-12-27
*
Replaced signed_parameters API with CONST_FLAG_SIGNED
Clifford Wolf
2013-12-04
*
Replaced RTLIL::Const::str with generic decoder method
Clifford Wolf
2013-12-04
*
Added proper dumping of signed/unsigned parameters to verilog backend
Clifford Wolf
2013-11-24
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Implemented $_DFFSR_ expression generator in verilog backend
Clifford Wolf
2013-11-21
*
Write yosys version to output files
Clifford Wolf
2013-11-03
*
Fixed handling of boolean attributes (backends)
Clifford Wolf
2013-10-24
*
Fixed handling of boolean attributes (kernel)
Clifford Wolf
2013-10-24
*
Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_
Clifford Wolf
2013-10-18
*
Added $sr, $dffsr and $dlatch cell types
Clifford Wolf
2013-10-18
*
Added -selected option to various backends
Clifford Wolf
2013-09-03
*
More explicit integer output in verilog backend
Clifford Wolf
2013-08-22
*
Implemented proper handling of stub placeholder modules
Clifford Wolf
2013-03-28
*
Avoid verilog-2k in verilog backend
Clifford Wolf
2013-03-21
*
More support code for $sr cells
Clifford Wolf
2013-03-14
*
Fixed a gcc compiler warning [-Wparentheses]
Clifford Wolf
2013-03-03
*
Added more help messages
Clifford Wolf
2013-03-01
*
initial import
Clifford Wolf
2013-01-05