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Author
Age
*
Added log_warning() API
Clifford Wolf
2014-11-09
*
Fixed generation of temp names in verilog backend
Clifford Wolf
2014-11-07
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor
Ahmed Irfan
2014-09-22
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\
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*
Sorting of object names in ilang backend
Clifford Wolf
2014-09-19
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*
Various bug fixes (related to $macc model testing)
Clifford Wolf
2014-09-06
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*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
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*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
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*
Using $pos models for $bu0
Clifford Wolf
2014-09-03
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*
Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...
Clifford Wolf
2014-09-01
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*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
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*
Changed backend-api from FILE to std::ostream
Clifford Wolf
2014-08-23
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*
Fixed AOI/OAI expr handling in verilog backend
Clifford Wolf
2014-08-16
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*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
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*
Renamed $lut ports to follow A-Y naming scheme
Clifford Wolf
2014-08-15
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*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
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*
Refactoring of CellType class
Clifford Wolf
2014-08-14
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*
Be more conservative with printing decimal numbers in verilog backend
Clifford Wolf
2014-08-02
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*
Improved verilog output for ordinary $mux cells
Clifford Wolf
2014-08-02
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*
No implicit conversion from IdString to anything else
Clifford Wolf
2014-08-02
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*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
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*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
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*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
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*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
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*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
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*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
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*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
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*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
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*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
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*
More RTLIL::Cell API usage cleanups
Clifford Wolf
2014-07-26
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*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
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*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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*
Various RTLIL::SigSpec related code cleanups
Clifford Wolf
2014-07-25
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*
Replaced more old SigChunk programming patterns
Clifford Wolf
2014-07-24
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*
Removed RTLIL::SigSpec::optimize()
Clifford Wolf
2014-07-23
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*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
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*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Clifford Wolf
2014-07-23
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*
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Clifford Wolf
2014-07-23
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*
SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
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*
SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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*
SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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*
Added "autoidx" statement to ilang file format
Clifford Wolf
2014-07-21
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*
Use functions instead of always blocks for $mux/$pmux/$safe_pmux in verilog b...
Clifford Wolf
2014-07-20
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*
Added support for $bu0 to verilog backend
Clifford Wolf
2014-07-20
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*
Merged OSX fixes from Siesh1oo with some modifications
Clifford Wolf
2014-03-13
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