yosys - Debian dgit repo for package yosys

	Commit message (Collapse)	Author	Age
*	Switched to Python 3	Clifford Wolf	2015-08-22
\|
*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16
\|
*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16
\|
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12
\| \| \| \|	This is based on work done by Larry Doolittle
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02
\|
*	Added output args to synth_ice40	Clifford Wolf	2015-05-26
\|
*	Verific build fixes	Clifford Wolf	2015-05-17
\|
*	Improved xilinx "bram1" test	Clifford Wolf	2015-04-09
\|
*	Added memory_bram "make_outreg" feature	Clifford Wolf	2015-04-09
\|
*	Xilinx DRAMS: RAM64X1D, RAM128X1D	Clifford Wolf	2015-04-09
\|
*	Towards DRAM support in Xilinx flow	Clifford Wolf	2015-04-09
\|
*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06
\|
*	Added Xilinx test case for initialized brams	Clifford Wolf	2015-04-06
\|
*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06
\|
*	Added "dffinit", Support for initialized Xilinx DFF	Clifford Wolf	2015-04-04
\|
*	Added "stat" to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
\|
*	Added final checks to "synth" and "synth_xilinx"	Clifford Wolf	2015-02-15
\|
*	Disabled (unused) Xilinx tristate buffers	Clifford Wolf	2015-02-04
\|
*	no support for 6-series xilinx devices	Clifford Wolf	2015-02-01
\|
*	Removed old XST-based xilinx examples	Clifford Wolf	2015-02-01
\|
*	Added Xilinx example for Basys3 board	Clifford Wolf	2015-02-01
\|
*	Added missing ports and parameters to xilinx brams	Clifford Wolf	2015-02-01
\|
*	Fixed xilinx FDSE sim model	Clifford Wolf	2015-01-24
\|
*	Various cleanups in xilinx techlib	Clifford Wolf	2015-01-18
\|
*	Refactoring of memory_bram and xilinx brams	Clifford Wolf	2015-01-18
\|
*	Added synth_xilinx -retime -flatten	Clifford Wolf	2015-01-17
\|
*	Added MUXCY and XORCY support to synth_xilinx	Clifford Wolf	2015-01-17
\|
*	Added dff2dffe to synth_xilinx	Clifford Wolf	2015-01-16
\|
*	Added more FF types to xilinx/cells.v	Clifford Wolf	2015-01-16
\|
*	Fixed xilinx bram clock inverted config	Clifford Wolf	2015-01-16
\|
*	Added FF cells to xilinx/cells_sim.v	Clifford Wolf	2015-01-16
\|
*	Added Xilinx MUXF7 and MUXF8 support	Clifford Wolf	2015-01-15
\|
*	Various cleanups in synth_xilinx command	Clifford Wolf	2015-01-13
\|
*	Added add_share_file Makefile macro	Clifford Wolf	2015-01-08
\|
*	added minimalistic xilinx sim models	Clifford Wolf	2015-01-08
\|
*	More Xilinx bram cleanups	Clifford Wolf	2015-01-07
\|
*	Cleanups in xilinx bram descriptions	Clifford Wolf	2015-01-07
\|
*	Xilinx RAMB36/RAMB18 memory_bram support complete	Clifford Wolf	2015-01-06
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
\|
*	small fix in xilinx/brams.v	Clifford Wolf	2015-01-06
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
\|
*	Various small improvements to synth_xilinx	Clifford Wolf	2015-01-06
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-06
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-05
\|
*	Towards Xilinx bram support	Clifford Wolf	2015-01-04
\|
*	Progress in memory_bram	Clifford Wolf	2014-12-31
\|
*	Added memory_bram (not functional yet)	Clifford Wolf	2014-12-31
\|
*	namespace Yosys	Clifford Wolf	2014-09-27
\|
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15
\|