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Author
Age
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
namespace Yosys
Clifford Wolf
2014-09-27
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
*
Fixed a bug in "add -global_input"
Clifford Wolf
2013-11-21
*
Added "add" command (only wires for now)
Clifford Wolf
2013-11-20