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Author
Age
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
*
Fixes in "hilomap" help message
Clifford Wolf
2014-10-08
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namespace Yosys
Clifford Wolf
2014-09-27
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Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
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Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
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Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
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Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
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Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
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Use only module->addCell() and module->remove() to create and delete cells
Clifford Wolf
2014-07-25
*
Fixed all users of SigSpec::chunks_rw() and removed it
Clifford Wolf
2014-07-23
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SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...
Clifford Wolf
2014-07-22
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SigSpec refactoring: using the accessor functions everywhere
Clifford Wolf
2014-07-22
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SigSpec refactoring: renamed chunks and width to __chunks and __width
Clifford Wolf
2014-07-22
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Replaced depricated NEW_WIRE macro with module->addWire() calls
Clifford Wolf
2014-07-21
*
Added hilomap command
Clifford Wolf
2014-01-19